Power Switch with Source-Bias Mode for on-chip Powerdomain Supply Drooping

ABSTRACT

This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit supplied by a voltage regulator. In a normal mode a PMOS source-drain channel connects the voltage regulator power to the circuit module power input or isolates them dependent upon a power switch input. In a low power mode a second PMOS connected between the first PMOS gate and output diode connects the first PMOS. This supplied the circuit module from the voltage regulator power as reduced in voltage by a diode forward bias drop. This lower voltage should be sufficient for flip-flops in the circuit module to retain their state while not guaranteeing logic operation. There may be a plurality of chain connected droop switch each powering a corresponding circuit module.

BACKGROUND OF THE INVENTION

A prior art System on Chip (SoC) employing semiconductor features sizes of 28 nm implements automatic dynamic voltage scaling (AVS) with an external voltage regulator. Typically the AVS is limited to a certain voltage range determined by the differential in voltages allowed between a static random access memory (SRAM) bit cell minimum voltage and surrounding logic. For this prior art device the AVS voltage is typically scaled between 1 V and 0.72 V.

The flip flop designs in the corresponding circuit library may retain their state at even lower voltages. In a known semiconductor manufacturing process, the retention voltage is around 0.5 V. Potential leakage current savings could be accomplished by lowering the voltage even below the typical automatic DVS scaled voltage. In an example digital signal processor of the Texas Instruments TMS320C6600 family, lowering the voltage below the AVS voltage could reduce the leakage current by 40 to 60% when the DSP is idle.

SUMMARY OF THE INVENTION

A power supply for an electronic circuit enables a low effort retention mode. During a normal mode a circuit module is supplied a first voltage sufficient for a controlled circuit to operate. During the low effort retention mode the circuit module is supplied with a second voltage lower than the first voltage. The second voltage is sufficient for flop-flops to retain their state but not sufficient to guarantee proper circuit operation. The two voltages can be produced by separate voltage regulators. The second voltage can be produced by a voltage drop (droop) from the first voltage. The preferred embodiment includes a System On Chip and two external voltage regulators or one external voltage regulators and an on-chip droop circuit for each circuit module.

In the preferred embodiment a single integrated circuit includes a circuit module and a droop switch circuit supplied by a voltage regulator. In a normal mode a PMOS source-drain channel connects the voltage regulator power to the circuit module power input or isolates them dependent upon a power switch input. In a low power mode a second PMOS connected between the first PMOS gate and output diode connects the first PMOS. This supplied the circuit module from the voltage regulator power as reduced in voltage by a diode forward bias drop. This lower voltage should be sufficient for flip-flops in the circuit module to retain their state while not guaranteeing logic operation. There may be a plurality of chain connected droop switch each powering a corresponding circuit module.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of this invention are illustrated in the drawings, in which:

FIG. 1 illustrates a prior art system on chip system driven by a voltage regulator to which this invention is applicable;

FIG. 2 illustrates a first embodiment of this invention employing two voltage regulators;

FIG. 3 illustrates a second embodiment of this invention employing a single voltage regulator where each controlled power domain includes a voltage drooping circuit;

FIG. 4 illustrates the inputs and outputs of a power switch including a voltage drooping circuit according to the second embodiment of this invention;

FIG. 5 illustrates the cooperation of a chain of the power switches illustrated in FIG. 4 are used;

FIG. 6 is a schematic diagram of an embodiment of the power switch including a voltage drooping circuit according to the second embodiment of this invention illustrated in FIG. 4;

FIG. 7 illustrates a practical embodiment of circuit 600 illustrated in FIG. 6; and

FIG. 8 illustrates another practical embodiment of circuit 600 illustrated in FIG. 6.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 illustrates a typical prior art SOC power management scheme. System on chip (SOC) 100 includes power state controller 101 and plural power domains 111, 112 and 113. Power domains 111, 112 and 113 represent parts of SOC 100 including useful circuits in separately controlled power domains. The number of such power domains and their exact function within SOC 100 are not important to this invention. External voltage regulator 120 supplies an adjustable voltage in the range from 1.1 V to 0.72 V from a power source. This power source may have a voltage of 3.3 V or of 1.8 V.

The state elements (flip flops and latches) within power domains 111, 112 and 113 may hold their state value at voltages as low as 0.5 V to 0.6 V. Typically the rest of SOC 100 circuits will not be functional at such a voltage. This could be due to the library characterization and timing closure not comprehending the lower voltage operation or the lower voltage could be outside the range of functional operation of SOC 100. Some part of SOC 100 may have to be functional all the time. These parts may include control power state sequencing circuits, clocks and the like. Thus the AVS input supply voltage to SOC 100 cannot be scaled to the lower voltage range of 0.5 V to 0.6 V. An entire separate power domain (typically implemented using power switches inside a physical design) can be lowered in voltage to the lower voltage range of 0.5 V to 0.6 V to implement a low effort retention scheme. Typically when a power domain is power-gated, the outputs are isolated, clocks are switched off etc. Upon entry into that mode, the voltage supply to the power domain can be lowered to enable a low voltage retention mode. This mode enables an additional retention state with very low effort and software can be modified to offer better idle/standby power management. As previously noted, most circuits will not operate at this reduced voltage. Because the power domain state is retained, recovery from the power down state to fully operation will be faster than recovery from a power OFF state.

This invention may be implemented in the following ways. A first embodiment employs multiple AVS power supplies. A second embodiment includes a single AVS power supply and all power domains capable of the low effort retention mode include internal power supply drooping to reach the lower voltage.

FIG. 2 illustrates an example of the first embodiment of this invention having plural AVSs. SOC 200 includes power state controller 201 corresponding to power state controller 101 illustrated in FIG. 1. SOC 200 typically includes plural power supply domains as illustrated in FIG. 1. FIG. 2 illustrates a single power domain 211 as an example of a power domain that does not employ the low effort retention mode. Power domain 211 receives electric power directly from first voltage regulator in the same manner as power state controller 201. SOC 200 may include plural such power domains. SOC 200 may further include one or more power domains which may enter the low effort retention mode. FIG. 2 illustrates power domain 213 as an example power domain that may enter the low effort retention mode. SOC 200 may include plural such power domains.

SOC 200 is supplied power by two AVSs. External first voltage regulator 221 supplies an adjustable voltage in the range from 1.1 V to 0.72 V from the power source. As described in conjunction with FIG. 1, this power source has a voltage of 3.3 V or of 1.8 V. Power from first voltage regulator 221 is supplied to power state controller 201, power domain 211 and to power supply multiplexer 212. Second voltage regulator 222 supplies an adjustable voltage in the range from 0.5 V to 1.1 V from a power source 120. This second voltage is supplied to power supply multiplexer 212.

Power supply multiplexer 212 determines which power supply powers power domain 213. During normal operations power supply multiplexer 212 selects power from first voltage regulator 221. On entering the low effort retention mode power supply multiplexer 212 selects power from second voltage regulator 222. As noted above power domain 213 is typically power-gated, the outputs are isolated, clocks are switched off on entering the low effort retention mode in a manner not shown in FIG. 2.

FIG. 3 illustrates the second embodiment of this invention. SOC 300 includes power state controller 301 similar to power state controller 101 illustrated in FIG. 1 and power state controller 201 illustrated in FIG. 2. FIG. 3 illustrates a single power domain 311 as an example of a power domain that does not employ the low effort retention mode. Power domain 311 receives electric power directly from first voltage regulator in the same manner as power state controller 301. SOC 300 may include plural such power domains. SOC 300 includes power domains with drooping 312 and 313. Each of power domains with drooping 312 and 313 receive electric power from external voltage regulator 321. Voltage regulator 321 is similar to voltage regulator 121 illustrated in FIG. 1 and first voltage regulator 221 illustrated in FIG. 2. Voltage regulator 321 receives 3.0 V or 1.8 V input power and supplies an adjustable voltage in the range from 1.1 V to 0.72 V. During normal operations power domains 312 and 313 operate on power at the received voltage without implementing the built-in voltage droop. On entering the low effort retention mode the droop circuits in power domains 312 and 313 reduce the voltage of the supplied power to the retention mode voltage of 0.5 V to 0.6 V.

Table 1 lists a comparison of the electric power consumed and the time needed to recover full operation for various operating modes. The normal mode is fully powered. The clock gated mode supplies the full voltage to the circuit but freezes the clock inputs. The retention mode is this invention. The power gated mode removes both electric power and clocks from the circuit.

TABLE 1 Mode Relative Power Consumed Recovery cycles/time Normal 1x   0/0 Clock Gated 0.8x 1 to 2 cycles/nS Retention Mode 0.1x to 0.3x few 10's of cycles/nS Power Gated  0.01x few 1000's of cycles/μS As shown in Table 1 this invention provides a good intermediate power level versus recovery time. This invention uses less power than clock gating the circuit and requires less recovery time than power gating the circuit.

State retention could be implemented in a SOC circuit using retention cells in the standard cell library. This technique is commonly used. This technique adds lot of effort including cell library development, characterization and power domain implementation. The on-chip supply drooping based retention of this invention implements full retention. With this invention cell library changes are limited to few standard cells. Thus this invention is scalable.

FIGS. 4, 5 and 6 illustrate a power switch used on a SOC to implement this invention. FIG. 4 is a block diagram showing the inputs and outputs. Power switch 400 receives a power source V_(DD) and generates a power output V_(DD) _(_) _(LSW). Power switch 400 receives inputs DROOPIN and PGODIN which control its operation. Power switch 400 is typically deployed in a chain of power switches connected together. The DROOPOUT output of one power switch supplies the DROOPIN input of a next power switch in the chain. The PGOODOUT output supplies the PGOODIN input of the next power switch in the chain. Power switch 400 operates as shown in Table 2.

TABLE 2 DROOPIN PGOODIN Mode 0 0 OFF 0 1 Normal 1 0 Retention Mode 1 1 Retention Mode

FIG. 5 illustrates an example 500 of the chain of switches 400 employed in the chain. The input signals DROOPIN and PGOODIN are supplied to corresponding inputs of the first power switch in the chain, power switch 510. As previously described, the DROOPOUT output of power switch 510 supplies the DROOPIN input of power switch 520 and the PGOODOUT output of power switch 510 supplies the PGOODIN input of power switch 520. FIG. 5 illustrates three power switches, 510, 520 . . . 570, but more or fewer power switches could be provided within the scope of this invention. Each power switch 510, 520 . . . 570 controls power supplied to a corresponding partition 515, 525 . . . 575 of power domain 505. FIG. 5 illustrates partitions 515, 525 . . . 575, but more or fewer partitions could be provided within the scope of this invention with each partition having a corresponding power switch. The chain of power switches 510, 520 . . . 570 prevents the source of signals PGOODIN and DROOPIN from exceeding a fan out limitation. Note that example 500 illustrated in FIG. 5 corresponds to a single power domain with drooping such as illustrated at 312 and 313 of FIG. 3.

FIG. 6 illustrates an exemplary diagram of circuit 600 implementing power switch 510, 520 . . . 570. The PGOODIN input drives invertor 610 consisting of a series connection of PMOS transistor 611 and NMOS transistors 612, 613 and 614. The PGOODIN input drives a common connection to the gates of PMOS transistor 611 and NMOS transistors 612, 613 and 614. The output of inverter 610, taken from between PMOS transistor 611 and NMOS transistor 612, drives the gate of PMOS transistor 621 in a manner further described below and the input of inverter 615. Due to the nature of PMOS and NMOS transistors, PMOS transistor 611 is conductive opposite to NMOS transistors 612, 613 and 614. Switches 601 and 602 control operation of circuit 600 in a manner detailed below.

The source-drain channel of PMOS transistor 621 is connected between the V_(DD) input and the V_(DD) _(_) _(LSW) output. The gate of PMOS transistor 621 is connected to the output of inverter 610 through the source-drain channel of NMOS transistor 733. Assuming that switch 601 is closed and switch 602 is open (DROOPIN=0), PMOS transistor 621 connects V_(DD) to V_(DD) _(_) _(LSW) on a 1 input on PGOODIN. PMOS transistor 612 isolates V_(DD) from V_(DD) _(_) _(LSW) on a 0 input on PGOODIN. Inverter 615 assures that the output PGOODOUT has the same digital sense as input PGOODIN to drive the next power switch in the chain. Capacitor 640 smoothes the output V_(DD) _(_) _(LSW).

The DROOPIN input signal is supplied to the input of inverter 631. The output of inverter 631 is supplied to the input of inverter 632. Inverter 632 assures that the output DROOPOUT has the same digital sense as input DROOPIN to drive the next power switch in the chain. Switches 601 and 602 are controlled as shown in Table 3.

TABLE 3 DROOPIN Switch 601 Switch 602 Inactive (0) Closed Open Active (1) Open Closed Switches 601 and 602 operate oppositely. When switch 601 is closed switch 602 is open and vice versa. When DROOPIN is inactive, switch 601 is closed and switch 602 is open. Circuit 600 operates according to the state of PGOODIN. For PGOODIN=1, circuit 600 supplies electric power to the corresponding partition by connecting the V_(DD) input to the V_(DD) _(_) _(LSW) output via PMOS 621. For PGOODIN=0, circuit 600 cuts off electric power from the corresponding partition. When DROOPIN is active, switch 601 is open and switch 602 is closed. Circuit 600 is no longer controlled by the state of PGOODIN. Instead, circuit 600 connects electric power to the corresponding partition by connecting the V_(DD) input to the V_(DD) _(_) _(LSW) output via a diode forward bias drop through the PMOS transistor 621. Thus V_(DD) _(_) _(LSW) is diode drop (about 0.2 V to 0.3 V) less than V_(DD). This enables the low retention voltage to be applied to the corresponding power module.

FIG. 7 illustrates a practical embodiment of circuit 600 illustrated in FIG. 6. Switches 601 and 602 are embodied by NMOS transistor 733 and PMOS transistor 734. The source-drain path NMOS transistor 733 connects the gate of PMOS transistor 621 to inverter 611 when DROOPIN is inactive (Normal mode) and is open otherwise. This embodies first switch 601. The source-drain path of PMOS transistor 734 connects the gate of PMOS transistor 621 to the second terminal of its source-drain path when DROOPIN is active (Retention mode) and is open otherwise. This embodies second switch 602.

Due to the nature of PMOS and NMOS transistors, NMOS transistor 733 is conductive opposite to PMOS transistor 734. When DROOPIN is 0, NMOS transistor 733 is conducting and NMOS transistor 734 is not conducting. Accordingly, the gate of PMOS transistor 621 is connected to the output of inverter 610 to be driven conductive or non-conductive according to the state of PGOODIN. As shown in Table 2 the corresponding power domain is driven OFF or NORMAL based upon the state of PGOODIN. Note when PGOODIN is 1, PMOS transistor 621 is conductive connecting the V_(DD) input to the V_(DD) _(_) _(LSW) output. When PGOODIN is 0, PMOS transistor 621 is non-conductive isolating the V_(DD) input from the V_(DD) _(_) _(LSW) output.

When DROOPIN is 1, NMOS transistor 733 is not conducting and NMOS transistor 734 is conducting. In this situation the state of PGOODIN is not controlling. The source-drain channel of NMOS transistor 734 connected the gate to PMOS transistor 621 to a terminal of its source-drain channel. PMOS transistor 621 connects the V_(DD) input to the V_(DD) _(_) _(LSW) output via a diode forward bias drop through the PMOS transistor 621. Thus V_(DD) _(_) _(LSW) is diode drop (about 0.2 V to 0.3 V) less than V_(DD). This enables the low retention voltage to be applied to the corresponding power module.

Selection of an NMOS type for transistor 733 and a PMOS type for transistor 734 is not required. Switch 601 could be embodied by a PMOS transistor. In order to preserve the states shown in Table 3, this PMOS transistor must be driven in an opposite phase than illustrated in FIG. 7. This opposite phase could be a connection of the gate of this transistor directly to DROOPIN at the input of inverter 631 or from the output of inverter 632. Switch 602 could be embodied by an NMOS transistor. This NMOS transistor must be driven in an opposite phase than illustrated in FIG. 7 such as directly by DROOPIN at the input of inverter 631 or from the output of inverter 632. The conductivity type (N channel or P channel) is not important as long as the states conform to Table 3.

FIG. 8 illustrates a further alternative for embodying switch 601. FIG. 8 is similar to FIG. 7 and like parts have like reference numbers. In FIG. 8 switch 601 is embodied by a parallel combination of NMOST transistor 733 and PMOS transistor 833. The gate of PMOS transistor 833 is connected to the DROOPIN input. PMOS transistor 833 pulls up the gate of PMOS transistor 621 to the full supply to turn off PMOS transistor 621 completely when DROOPIN=0 and PGOODIN=0. In the circuit of FIG. 8 NMOS transistor 733 ensures that when DROOPIN=0 and PGOODIN=1 gate of PMOS transistor 621 is fully pulled down to 0 V causing PMOS transistor 621 to fully conduct.

This embodiment of the invention does not require extra power supplies brought on-chip nor specialized register cell designs. Such specialized register cell designs are common across almost all other retention solutions. Such specialized register cell designs typically bring some additional complexity to those circuits including specialized clocking and control signaling or both. This embodiment of the invention uses a single custom power switch design with almost any standard cell library. Such power switches are robustly designed with respect to process, temperature and voltage (PTV) variations. This is the key differentiator of this solution.

This embodiment of the invention requires only one standard cell change in the power switch. Thus the design effort to adopt this embodiment of the invention is very low. Since this embodiment of the invention uses the power switch itself as the diode in the source biased mode, there is no additional area incurred in the power switch implementation. 

1.-12. (canceled)
 13. An electronic circuit comprising: a circuit module including at least one flip-flop having two states, said circuit module including a power input terminal; a voltage regulator connected to a power supply generating a first voltage sufficient for said at least one flip-flop to retain its state in said circuit module; a droop switch circuit connected to said first voltage regulator and said circuit module, having a low power mode input and a power switch input, said droop switch circuit including a first PMOS transistor having a first terminal of a source-drain channel connected to a power supply output of said first voltage regulator, a second terminal of said source-drain channel connected to said power switch input of said circuit module and a gate, a first switch having a first terminal connected to said first PMOS transistor and a second terminal, said first switch operable to be closed when a low power mode input is active and open when the low power mode input is active, a first inverter having an input connected to said power switch input and an output connected to said second terminal of said first switch, a second inverter having an input connected to said low power mode input and an output, and a second switch having a first terminal connected to said gate of said first PMOS transistor and a second terminal connected to said power switch output, said second switch operable to be open when the low power mode input is active and closed when the low power mode input is active.
 14. The electronic circuit of claim 13, wherein: said first inverter includes a second PMOS transistor having a first terminal of a source-drain channel connected to a power source, a second terminal of said source-drain channel connected to said output of said first inverter, and a gate connected to said input of said first inverter, a second NMOS transistor having a first terminal of a source-drain channel connected to said second terminal of said source-drain channel of said third PMOS transistor, a second terminal of said source-drain channel and a gate connected to said input of said first inverter, a third NMOS transistor having a first terminal of a source-drain channel connected to said second terminal of said source-drain channel of said second NMOS transistor, a second terminal of said source-drain channel and a gate connected to said input of said first inverter, a fourth NMOS transistor having a first terminal of a source-drain channel connected to said second terminal of said source-drain channel of said third NMOS transistor, a second terminal of said source-drain channel and a gate connected to said input of said first inverter.
 15. The electronic circuit of claim 13, wherein: said circuit module and said droop switch circuit are disposed on a single integrated circuit; and said voltage regulator is disposed external to said single integrated circuit.
 16. The electronic circuit of claim 13, wherein: said first switch comprises a first NMOS transistor having a first terminal of a source-drain channel connected to said first PMOS transistor, a second terminal of said source-drain channel connected to said output of said first inverter and a gate connected to said output of said second inverter.
 17. The electronic circuit of claim 13, wherein: said first switch comprises a first NMOS transistor having a first terminal of a source-drain channel connected to said first PMOS transistor, a second terminal of said source-drain channel connected to said output of said first inverter and a gate connected to said output of said second inverter, a second PMOS transistor having a first terminal of a source-drain channel connected to said first PMOS transistor, a second terminal of said source-drain channel connected to said output of said first inverter and a gate connected to said low power mode input.
 18. The electronic circuit of claim 13, wherein: said second switch comprises a second PMOS transistor having a first terminal of a source-drain path connected to said gate of said first PMOS transistor, a second terminal of a source-drain channel connected to said power switch output and a gate connected to said output of said second inverter.
 19. An electronic circuit comprising: a plurality of circuit modules, each circuit module including at least one flip-flop having two states, each circuit module including a power input terminal; a voltage regulator connected to a power supply generating a first voltage sufficient for said at least one flip-flop to retain its state in each of said circuit modules; a plurality of droop switch circuits, each droop switch circuit connected to said voltage regulator and to a corresponding one of said circuit module, having a low power mode input, a power switch input, a low power mode output and a power switch output, each said droop switch circuit including a first PMOS transistor having a first terminal of a source-drain channel connected to a power supply output of said first voltage regulator, a second terminal of said source-drain channel connected to said power switch input of said circuit module and a gate, a first switch having a first terminal connected to said first PMOS transistor and a second terminal, said first switch operable to be closed when a low power mode input is active and open when the low power mode input is active, a first inverter having an input connected to said power switch input and an output connected to said second terminal of said source-drain channel of said first NMOS transistor, a second inverter having an input connected to said low power mode input and an output, a second switch having a first terminal connected to said gate of said first PMOS transistor and a second terminal connected to said power switch output, said second switch operable to be open when the low power mode input is active and closed when the low power mode input is active, a third inverter having an input connected to said output of said first inverter and an output connected to said power switch output, and a fourth inverter having an input connected to said output of said second inverter and an output connected to said a low power mode output, wherein said plurality of droop switch circuits are connected in a chain with said low power mode output of each droop switch except a last in said chain connected to said low power mode input of a next droop switch circuit in said chain and said power switch output of each droop switch except a last in said chain connected to said power switch input of a next droop switch circuit in said chain.
 20. The electronic circuit of claim 19, wherein: said first inverter includes a third PMOS transistor having a first terminal of a source-drain channel connected to a power source, a second terminal of said source-drain channel connected to said output of said first inverter, and a gate connected to said input of said first inverter, a second NMOS transistor having a first terminal of a source-drain channel connected to said second terminal of said source-drain channel of said third PMOS transistor, a second terminal of said source-drain channel and a gate connected to said input of said first inverter, a third NMOS transistor having a first terminal of a source-drain channel connected to said second terminal of said source-drain channel of said second NMOS transistor, a second terminal of said source-drain channel and a gate connected to said input of said first inverter, a fourth NMOS transistor having a first terminal of a source-drain channel connected to said second terminal of said source-drain channel of said third NMOS transistor, a second terminal of said source-drain channel and a gate connected to said input of said first inverter.
 21. The electronic circuit of claim 19, wherein: each of said plurality of circuit modules and each of said plurality of droop switch circuits are disposed on a single integrated circuit; and said voltage regulator is disposed external to said single integrated circuit.
 22. The electronic circuit of claim 19, wherein: said first switch comprises a first NMOS transistor having a first terminal of a source-drain channel connected to said first PMOS transistor, a second terminal of said source-drain channel connected to said output of said first inverter and a gate connected to said output of said second inverter.
 23. The electronic circuit of claim 19, wherein: said first switch comprises a first NMOS transistor having a first terminal of a source-drain channel connected to said first PMOS transistor, a second terminal of said source-drain channel connected to said output of said first inverter and a gate connected to said output of said second inverter, a second PMOS transistor having a first terminal of a source-drain channel connected to said first PMOS transistor, a second terminal of said source-drain channel connected to said output of said first inverter and a gate connected to said low power mode input.
 24. The electronic circuit of claim 19, wherein: said second switch comprises a second PMOS transistor having a first terminal of a source-drain path connected to said gate of said first PMOS transistor, a second terminal of a source-drain channel connected to said power switch output and a gate connected to said output of said second inverter. 